@atoponce I want to say that there was a high read throughput storage appliance at a HPC facility that I worked at that used raid3 in its back end, but I don't remember the details!
Any and all answers are greatly appreciated. No judgement whatsoever. Asking this for research on a WIP article:
Do you #selfhost ? If so:
- What do you host yourself?
- Do you use an existing toolchain (Ansible/Puppet scripts, Yunohost, etc)?
- Do you run it bare metal, virtualized or containerized? Which one?
@h3artbl33d I #selfhost email on 2 domains, along with a blog, websites for those domains, matrix, mastodon gemini, gitea and nextcloud. I have mostly done it via following along with install guides, some I have ansible-ified so it can be deployed anywhere. I started with a few KVMs but have moved to an LXC container for each service over the last 18 months.
I really need to get my mail services sorted out though, it was the first thing I did, so it's a bit messy and hard to move around!
@tindall I've never looked it up, but from context it seems its the stuff people do, a face people put on, so to speak, so they don't have to suffer further from their lack of privilege in a relationship. Those with privilege do not even recognise this as work that needs to be done.
Please boost if you like #haskell, niche programming languages, retro computing, or smallnet, please. I'm looking for online nerd friends.
andrew lee just seized over 700 channels on freenode because they mentioned libera.chat in their topic.
This includes projects like openbsd, wikimedia, FOSDEM, etc.
https://archive.is/uHw1g shows 720 channels that match what is being checked.
here's an example log: https://gist.github.com/pushcx/ab2a1d5b1d18e964c581ef18ccb3a79f
boost this if you care about foss in any way.
The issue isn't static logic. The issue is divorcing instruction decoding from instruction set design to attain performance goals not originally built into the ISA.
It takes, for example, several clock cycles just to decode x86 instructions into a form that can then be readily executed. Several clocks to load the code cache. Several clocks to translate what's in the code cache into a pre-decoded form in the pre-decode cache. Several clocks to load a pre-decode line into the instruction registers (yes, plural) of the instruction fetch unit. A clock to pass that onto the first of (I think?) three instruction decode stages in the core. Three more clocks after that, you finally have a fully decoded instruction that the remainder of the pipelines (yes, plural) can potentially execute.
Of course, I say potentially because there's register renaming happening, there's delays caused by waiting for available instruction execution units to become available in the first place, there's waiting for result buses to become uncontested, ...
The only reason all this abhorrent latency is obscured is because the CPU literally has hundreds of instructions in flight at any given time. Gone are the days when it was a technical achievement that the Pentium had 2 concurrently running instructions. Today, our CPUs, have literally hundreds.
(Consider: a 7-pipe superscalar processor with 23 pipeline stages, assuming no other micro-architectural features to enhance performance, still offers 23*7=161 in-flight instructions, assuming you have some other means of keeping those pipes filled.)
This is why CPU vendors no longer put cycle counts next to their instructions anymore. Instructions are pre-decoded into short programs, and it's those programs (strings of "micro-ops", hence micro-op caches, et. al.) which are executed by the core on a more primitive level.
Make no mistake: the x86 instruction set architecture we all love to hate today has been shambling undead zombie for decades now. RISC definitely won, which is why every x86-compatible processor has been built on top of RISC cores since the early 00s, if not earlier. Intel just doesn't want everyone to know it because the ISA is such a cash cow these days. Kind of like how the USA is really a nation whose official measurement system is the SI system, but we continue to use imperial units because we have official definitions that maps one to the other.
Oh, but don't think that RISC is immune from this either. It makes my blood boil when people say, "RISC-V|ARM|MIPS|POWER is immune."
No, it's not. Neither is MIPS, neither is ARM, neither is POWER. If your processor has any form of speculative execution and depends on caches for maintaining instruction throughputs, which is to say literally all architectures on the planet since the Pentium-Pro demonstrated its performance advantages over the PowerPC 601, you will be susceptible to SPECTRE. Full stop. That's laws of physics talking, not Intel or IBM.
Whether it's implemented as a sea-of-gates in some off-brand ASIC or if it's an FPGA, or you're using the latest nanometer-scale process node by the most expensive fab house on the planet, it won't matter -- SPECTRE is an artifact of the micro-architecture used by the processor. It has nothing whatsoever to do with the ISA. It has everything to do with performance-at-all-costs, gotta-keep-them-pipes-full mentality that drives all of today's design requirements.
I will put the soapbox back in the closet now. Sorry.
@freakboy3742 I'm privileged enough to be able to give my preteen on an old MacBook air. It's a bit slow these days but does still function enough for teaching purposes!
@ifixcoinops if you can, get a proper desoldering gun, one with a vacuum pump. Makes removing the switches so much easier. I have a fait bit of through hole soldering experience so didn't find the putting on switches part too hard! Getting alignment exactly correct was tricky though 🥺
Ok Winamp isn't too bad!